Various integrated circuit chips are timed using two separate clock systems, one a low-frequency system and the second a high frequency system. Typically, two oscillators are incorporated into these systems to supply the dual timing rates. Since oscillators consume power and space, it is generally advantageous to eliminate one of the oscillators and generate two timing signals from a single oscillator.
Two techniques are used to generate two timing signals from a single oscillator. One technique involves usage of a high-frequency oscillator. A low-frequency timing signal is formed using a frequency divider to divide the high-frequency timing signal. Unfortunately, in circuit operating modes which utilize only low-frequency timing signals, a high-frequency oscillator is very wasteful of power. Generally a special high-frequency oscillator is needed to limit power consumption to a reasonable level.
A second technique for generating two timing signals from a single oscillator is to utilize only a low-frequency oscillator. A high-frequency timing signal is formed by incorporating a frequency multiplier to multiply the low-frequency signal. Typically most implementations of a frequency multiplier include a phase-locked loop (PLL) circuit. However, a PLL implementation generally requires special circuit techniques such as charge pump circuits to achieve a high multiplication factor. Another disadvantage of PLL implementations is a long delay incurred during frequency locking. Furthermore, PLL implementations are potentially unstable circuits. PLL circuits unacceptably consume a large area of an integrated circuit. In addition, PLL implementations have great difficulty in achieving large multiplication factors. A potential advantage of a phase-locked loop implementation is that the phase between the high and low-frequency timing signals is correlated. However, this advantage is rarely exploited in a frequency multiplier circuit.